FastChip 2.3.0 Tutorial for the E5 CSoC Device

Scope

This tutorial introduces you to the basic operations and the design flow of FastChip. It guides you through a sample project using the Triscend E5 Configurable System on Chip (CSoC).

In Part 1 of this tutorial you will:

In Part 2 of this tutorial you will:

Design Overview

Figure 1.  A block diagram of the E5 tutorial design.

The admittedly simple tutorial design, shown in Figure 1, introduces a number of major FastChip concepts.  When complete, the design operates on the one of the various Triscend E5 development boards.

In the example design, the E5’s dedicated Watchdog Timer generates an interrupt whenever the timer expires.  The interrupt then proceeds to the embedded 8051 microcontroller (MCU) via the interrupt controller.  The 8051 then services the interrupt and increments a value in a register called RESULT.  The contents of the RESULT register appears on the E5 board’s 7-segment LED display.

The RESULT register is actually implemented in the E5’s Configurable System Logic (CSL).  The processor communicates to the RESULT register via the dedicated Configurable System Interconnect (CSI) bus.  In the tutorial, the RESULT register is built using a soft IP  module function called a Command Register.  Soft modules are pre-defined, pre-verified logic cores or functions, which are provided free-of-charge with FastChip.

In order to view the contents of the RESULT register on the E5 Evaluation Board, the RESULT register connects to a 7-segment display decoder, called D1.  The 7-segment display decoder is another FastChip soft module.  The 7-segment decoder displays the four-bit output from the RESULT register as a hexadecimal character.  The display decoder contains seven output pins that will eventually connect directly to the 7-segment LED on the development board.

Design Flow

CSoC Development

1)       Invoke FastChip

2)       Start a new project

3)       Set up dedicated resources

·         Watchdog Timer

·         Interrupt Controller

4)       Use soft IP modules from the Triscend library

·         Command Register

·         7-Segment display decoders/drivers

5)       Import and use a custom Module

·         Toggler

6)       Generate initialization code for your application

7)       Assign I/O

8)       Bind the project

Software Application Development

9)       Develop the application software

10)   Compile and link your application

Download Design

11)   Invoke FastChip Device Link Utility

12)   Create CSoC configuration image

13)   Download CSoC configuration image

In-System Debugging

14)   In-System Debugging using FastChip Device Link Utility

15)   In-System Debugging using the Keil Debugger

PART I:  Designing with the FastChip Graphical Environment

STEP 1.Invoke FastChip

Invoke the FastChip software by double clicking the FastChip desktop icon or by choosing Start à Programs à Triscend FastChip 2.3.0 à Triscend FastChip 2.3.0.

FastChip is a Java-based application and it may take a few moments for your computer to load the Java virtual machine.  FastChip displays a welcome splash screen as it loads.

After the splash screen, FastChip displays a welcome dialog box describing FastChip and its capabilities.  If you wish to hide this dialog box in the future, uncheck the Show this window … option at the bottom of the dialog box.  After reading the messages in this dialog box, click Close to continue.

Unless you have already licensed your version of FastChip, an evaluation license window appears describing the capabilities of the evaluation—or unlicensed—version of FastChip.  The evaluation version has all the same capabilities of the full, licensed version of FastChip except that it is limited to designs containing 256 or less Configurable System Logic (CSL) cells.  The tutorial design functions on both the full and the evaluation versions.  After reading the messages in this dialog box, click Close to continue.

By default, FastChip opens the last used FastChip project when you start.  You can change the start-up behavior of FastChip by selecting Tools à FastChip Options change the Default Project Opening settings in the Miscellaneous Setting panel.

STEP 2.  Start a New Project

You can create FastChip projects in any existing directory on your machine.  By default, FastChip uses <FastChip Install directory>\Projects directory, which is the recommended location.  Using the default installation settings, the project directory will be in the following location.

<drive>:\Triscend\FastChip\Projects

Three example projects are installed in this directory.  One of the examples, MyDesignE5, is similar to the tutorial project you are going to create

To create a new project, select File à New Project from the menu bar.

Enter “MyFirstE5” as the design name in the Project Name field.  The project is created in the default location unless you change the file settings under Project Location.  Create this project in the default location.

The default device selected by FastChip is the TE520S40-40Q, which is the same device used on the Triscend E5 Evaluation Board and the older, now obsolete E5 Development Board.

 

If using the XESS myCSoC board, select an E505 CSoC device, in the 128-pin LQFP package, and the 25 MHz speed grade (Part: TE505S16-25L).

 

The tabs on the right side of the dialog box show various characteristics of the selected device.  Click the Available Resources tab to display the design resources inside a TE520.  The TE520 has 2,048 Configurable System Logic (CSL) cells, 128 address Selectors, up to 154 user-defined Programmable Input/Ouput (PIO) pins, and six global buffers (GBUFs).  Click OK to continue.

FastChip Main Window

After creating a new project and selecting the target device, FastChip displays the main window.

The figure below shows how FastChip should appear on your screen by default.  If it does not appear like this figure, select View à CSoC.

The FastChip main window contains the following areas:

Menu Bar:  Displays the various commands supported by FastChip

Toolbar: Contains shortcut icons for the most commonly used tools to build your project

Dedicated Resources:  Contains icons representing the dedicated resources on the E5 CSoC, including the various peripherals.  These functions are always present in a FastChip project

Module Library:  Lists the Triscend soft modules function provided with FastChip, as well as any modules you created by importing logic designs from schematic capture or logic synthesis.

CSL Window:  Contains the modules you selected and configured.  These modules are implemented using the Configurable System Logic (CSL) resources on the CSoC.

Resource Estimate:  Displays the estimated resource requirements for the modules instantiated in CSL window.  The actual number of resources required is determined by executing Bind and detailed in the project report.

STEP 3.  Set up Dedicated Resources

Across the top portion of the FastChip window is the Dedicated Resources area.  The dedicated resources are the pre-defined functions within every E5 CSoC device.

This sample application uses the E5’s watchdog timer to generate an interrupt to the embedded 8051 microcontroller.

Setting up the Watchdog Timer

From the Dedicated Resources area, click the Watchdog.

This example application uses the E5’s internal ring oscillator as the clock source because it is available across the various E5 development solutions.  The frequency of the ring ranges between 5 MHz to 20 MHz.

Select a Timer Interval of 8,388,608 clock cycles, which equates to a period of somewhere between about 0.5 and 1.5 seconds.  The precise period doesn’t matter for this design example.

Click Enable watchdog timer interrupt so that the Watchdog Timer generates an interrupt when the timer expires.

To see how FastChip configures the Watchdog Timer, click the View Header button at the bottom of the dialog box.  Scroll through the program listing to see the various Watchdog Timer registers.  The ‘C’ code appears at the bottom of the listing.

You can either include this initialization routine in your design “as is”, write your own, or use the FastChip-created file as a starting point.

Click Close to exit the View Header dialog box.

Click OK to program the Watchdog Timer values.

Setting up the Interrupt Controller

The Watchdog Timer interrupt connects to the 8051 through the 8051’s Interrupt Controller.  Click the ICU button to configure the Interrupt Controller.

Most of the 8051’s interrupts are globally enabled via a single control bit, called EA.  Check the Enable all interrupts option so that the Watchdog Timer interrupt connects to the 8051.

Click OK.

STEP 4.  Selecting and Configuring Soft IP Modules

This design example uses two modules, selected directly from the Triscend soft IP module library.

Command Register

A command register is a read/write register connected to the Configurable System Interconnect (CSI) bus. It is memory mapped, such that the processor and another bus master can write to it or read from it.  It is found in the Module Library tree under Peripherals à Control.

Alternatively, type “Comm” in the Module library text box, which highlights the Command Register module.

This example project uses a command register to control the 7-segment LED driver, which in turn connects to the 7-segment LED on the E5 Evaluation Board.  Double-click the Command Register module or optionally, drag and drop it into the CSL window.  If you drag and drop the module, click the associated icon in the CSL window.  This action opens the Command Register edit dialog box.

To view more information on how the Command Register module operates, click the Help button at the bottom of the dialog box.  Doing so invokes the context-sensitive online help.

Rename the module by typing “RESULT” in the Component Name text box.  Then rename the output signal bus connection for port Q to a new name by typing “RESULT“ in the connection box to the right of the Q output port.

The beauty of programmable logic is that your application uses only the amount of logic required to implement your design.  The tutorial design only requires a 4-bit register to hold the hexadecimal character displayed on the LED.  Consequently, tailor the Command Register to use only four bits.  Click the Component Width spinner buttons or enter a text value, ultimately setting the value to ‘4’.  Note that FastChip automatically completes the name of the Q output to RESULT[3:0].

Click the Properties tab.  Here, you can enter the symbolic address for the Command Register address.  You can also define the physical address for the command register.  However, FastChip is designed to support design re-use and easy integration.  Consequently, FastChip can automatically assign addresses for your application and pass the address assignments to your favorite 8051 compiler.  By assigning just a symbolic name, you let FastChip handle the mundane details of creating a memory map for your application.

Enter “RESULT” in the Symbolic Address text box.  Later in the tutorial, FastChip will generate a header file for the ‘C’ compiler.  The Generate function allocates this symbol to an unused address location.  Your source code can include the generated header and refer to this command register by its symbolic name, RESULT.

Click OK to complete configuration of the RESULT Command Register.  FastChip creates a custom-made module called RESULT in the CSL window, based on your settings.  Note that the Resource Estimate area shows that the design, so far, uses just four out of 2,048 available CSL cells and one of the 128 CSI bus address selectors.

7-Segment Display Driver

This project requires a 7-segment display driver to show the value of the RESULT register using the 7-segment LED on the E5 Evaluation Board.  To locate the 7-Segment Driver, type “7” in the Module Library text box.  FastChip finds and highlights the 7-Segment Driver module.

Double-click the 7-Segment Driver in the Module Library. Rename the Component Name to D1.

The input to the 7-segment module is a four-bit value.  The 7-segment module converts this four-bit digital value into the appropriate hexadecimal display on the 7-segment LED.  In this design, connect the output of the RESULT register to the Hex port.  There are a few ways to complete the connection.  The most obvious is simply to type the name “RESULT[3:0]” in the Hex input port text box.  However, you may not always remember the name of the desired connection.

Another approach is to use FastChip’s connection browser.  From within the 7-segment driver dialog box, click the magnifying glass icon next to the Hex input port text box.  There are two views of the connections within the design; the Hierarchical View shows all connections as a tree while the Flat View shows the connections alphabetically.

To see the signals connected to the RESULT register, click the RESULT folder icon.  Then choose the Q port, revealing the signals connected to the output port.  The signals are listed as a four-bit bit bus called RESULT[3:0] and as individual signals RESULT[3] through RESULT[0].  You could either select RESULT[3:0] or hold down the shift key and select the four individual nets.

Now choose the Flat View option.  Because this input port expects a multi-bit value, FastChip only displays multi-bit nets by default.  Play around a bit by clicking on the Show single-bit nets option and the Port connections option.  Also, try the Find function.  Finally, select the bus called RESULT[3:0] and click OK when finished.

Click the Properties tab.  The Triscend E5 Evaluation Board and the earlier E5 Development Board both used common cathode LED displays.  A logic Low applied to an LED segment lights the segment.   No modification is required.

 

The XESS myCSoC board uses a common anode LED display.  Select the Common anode option if you are using the myCSoC board.

 

Click OK to return to the CSL window, and notice that D1 has been added to the CSL window and that seven I/O pins are now used.

Various FastChip Features

Let the cursor linger over the D1 module icon.  FastChip displays a pop-up tool tip that shows how the D1 module is configured and connected.  This allows you to quickly review the properties of a module without clicking on it.  Also, note the small black arrow to the right of the RESULT module.  This indicates that RESULT drives a signal into D1.  This information is also shown in the tool tip.  Under the Connections sub-heading, note that the Hex port connects to a bus called “RESULT[3:0] (Driven by RESULT.Q)”, meaning that the ‘Q’ output port of the module named “RESULT” drives a bus called “RESULT[3:0]”.

To demonstrate a few other FastChip capabilities, click your right mouse button while the cursor is over the D1 module to reveal the module menu.  Select Duplicate Module Instance.

This duplicates the D1 module under a new component name 7seg_A, including all module settings and connections.  If you were to use this module, you probably want to edit it and modify some of the connections.

The tutorial does not require this new component.  To delete the module, place the cursor over the 7seg_A module and click the right mouse button to reveal the module menu.  This time, however, select Delete Module Instance.  FastChip then displays a confirmation dialog box asking if you really want to delete it.  Click Yes.  Once deleted, there is no undo command in FastChip.

At this point, the tutorial design has just two modules, resulting in a fairly sparse and straightforward CSL window display.  However, a design with many modules can become confusing.  FastChip allows you to reorder the modules in the display window so that you can group associated functions together.  To relocate a module, follow the steps shown below.

Click and hold the left mouse button over the module.

 

Drag and drop the module to the desired location.

 

Release the mouse button.

 

 

 

FastChip also provides an Auto Arrange feature that rearranges the modules so that the inputs to a specific module are above and the to left and outputs from a module are on the right or below.  Right click on the RESULT module and select Auto Arrange from the menu.  FastChip rearranges the modules by their connection.

At this point, the custom logic design for this simple design example is complete.  Select File à Save Project to save your design to disk.

STEP 5.   Import and Use a Custom Module

Before beginning this next section, copy the entire contents of the 3rdParty folder from the MyDesignE5 project directory into your tutorial project directory.  If you installed FastChip in the default locations and used the same project name as used throughout this tutorial, copy the folder…

C:\Triscend\Projects\MyDesignE5\3rdParty

… to …

C:\Triscend\Projects\MyFirstE5\

So far, all of the CSL logic functions were created using soft modules from the FastChip library.  While the library is extensive, it in no way covers all the potential functions that a designer may wish to implement.  To address this, FastChip allows you to import functions created with third-party logic design packages, such as schematic capture and logic synthesis.

Supported Logic Design Packages

The logic design software packages that currently support Triscend include …

·         Cadence/OrCAD Capture schematic capture, versions 7.2 and later

·         Innoveda/ViewDraw schematic capture

·         Synplicity Synplify logic synthesis, versions 6.2 and later

·         Synopsys FPGA Compiler II and FPGA Express logic synthesis, versions 3.4 and later

You can find additional information on using third-party design tools in the following Acrobat file …

Third_Party_Design_Methodology.pdf

stored in the following directory …

C:\Triscend\FastChip\Docs\Technical Documents.

All these tools require a Triscend-specific design library for optimal results.  For the Synplify and the FPGA Compiler II logic synthesis packages, the synthesis vendor provides the design library.  For schematic capture, Triscend provides the design libraries.

The schematic capture libraries are found under

C:\Triscend\FastChip\Data\Libraries\Schematic

Documentation on the libraries is available under

C:\Triscend\FastChip\Docs\Technical Documents.

as the two following Acrobat files …

Triscend_Primitives.pdf

Triscend_Schematic_Macros.pdf

The various third-party logic design packages create an EDIF 2.0.0 netlist file, which FastChip can read and convert to a custom-created soft module.  The next few steps describe the process to import an EDIF design.

Creating a Custom ‘heartbeat’ Module

In this example, assume that we want to create a custom logic function that toggles the decimal point on the LED display every time that the processor writes to the RESULT register.  The logic design is purposely trivial, as shown in the OrCAD Capture schematic below.

Essentially, when TOGGLE is High, the flip-flop Q toggles on the rising edge of BUSCLK.  The flip-flop output, Q, connects to an output pad called BEAT.  The source for BUSCLK is the CSI bus clock output, shown connecting to the CSI bus primitive, also called BUSCLK.  All CSI bus primitives have a 128-bit bus port just for simulation purposes.  The bus, SIM[127..0], does not actually appear in the graphical interface created by FastChip for the module.  Neither does the port called BEAT because it is already connected to an output pad.  The port called TOGGLE is an unconnected input port.  This port will appear in the graphical module interface.

Importing the Design

Assume that this schematic has already been saved as an EDIF file.  To bring this function into FastChip, click the Import button from the toolbar.

           

The resulting dialog asks you to specify the name of the EDIF netlist file.  Click Browse.

In the resulting file chooser dialog box, search for and select the file called heartbeat.edn under the directory …\3rdParty\EDA.  Click OK when finished.

The name of the EDIF netlist file appears in the Import dialog box.  By default, FastChip uses the name of the imported file as the name of the newly-created module.  The dialog allows you to specify another name and allows you to specify where the imported module will be placed.  For this example, use the default settings and click OK.

FastChip reads the specified EDIF netlist file, then flattens the logic, and then performs a design-rule check (DRC) for errors.  Click Close.

FastChip saves the imported function in the soft module library under Imported.  Unlike the remainder of the library, the Imported library directory is unique to this design.  It contains any and all imported functions specifically for this project.  Because the design is imported as a module, you can instantiate the same module any number of times within a design.

Using the New Module

To use the newly imported module, double-click on heartbeat in the Module Library area.

Customize the heartbeat module by typing “TOGGLER” as the Component Name.  Connect the TOGGLE input to a new signal by typing “UPDATE” in the connection port text box.  Click OK when finished.

Observe that the module was added to your CSL window and that the number of resources increased.

Connect the new TOGGLER module to the RESULT register.  Click the RESULT module to edit its settings.

The RdSel and WrSel outputs on the RESULT module are optional, and as such, there is an option box to the right of these outputs.  Check the box next to WrSel, enabling the connection text box.  The WrSel signal goes High whenever the RESULT register is written.

Type “UPDATE” in the text box to connect to the signal that drives the TOGGLER module.  Click OK.

Other Imported Library Options

FastChip allows you to perform various functions on a library module.  Imported modules support four functions while the standard FastChip library only supports adding and exporting a module.

To operate on a library module, click the right mouse button on the selected module.  The resulting menu allows up to four different functions.

·         Add Module Instance opens the module edit dialog and will add the module to your CSL logic when you click OK.

·         Re-import Module is useful after modifying an imported module and created a new EDIF file.  This option re-imports the new EDIF file based on the previous import settings.

·         Delete Module removes an imported module from the library tree.

·         Export Module allows you to create a Verilog or VHDL simulation model for the module, based on the module’s parameter settings.

STEP 6.  Generate Address Assignments, Header File for Your Application

FastChip generates C or assembly source code with declarations for the addressable registers in the configurable logic, such as the symbolic address RESULT in the command register soft module.

In addition, you can instruct FastChip to generate initialization functions for the dedicated resources.  Some of the dedicated resource dialog boxes allow you to specify the desired startup state of the dedicated resources.  You can selectively enable the Generate Code option to instruct FastChip to include functions for setting up the special function registers (SFR) associated with that dedicated resource in the generated source code.

At this time, no other Dedicated Resources need to be configured, and you can disable the Generate Code options in them to reduce the already modest code size of the generated source code.

Click the Generate button to invoke the Generate Code dialog box.  For the E5 CSoC, if the project name is more than 8 characters long, the file name is truncated.  This is because some of the 3rd party vendor software only supports 8.3 notation file names.  Consequently, Generate truncates the name MyFirstE5 to MyFirstE.

           

FastChip generates two files as shown below.

MyFirstE.h
This file contains necessary macro definitions and all the external address declarations for soft modules. It also contains prototypes for the dedicated resources initialization functions.

MyFirstE.c
This file contains necessary macro definitions, address declarations for soft modules, and function definitions of the dedicated resources initialization functions.

Earlier in the design example, the Command Register was given the symbolic address RESULT.  In order to pass the symbol and address of this register to your compiler, FastChip generates a ‘C’-language header file with declarations for the addressable registers in the configurable logic.

Save the generated file in the default location.  Click OK when finished.

During Generate, FastChip examines all the registers created in the CSL logic, allocates an address to each, and notes the address in the associated header file for your 8051 compiler.  A snippet from the header file is shown below.

 

/* add <FastChip install directory>\include to the compiler include path */

#include <TE5_CSOC.h>

 

// ========= BEGIN SOFT MODULE REGISTER DECLARATIONS ======

    CHAR_XDATA (RESULT,0xefff)

// ========== END SOFT MODULE REGISTER DECLARATIONS =======

STEP 7:  Assign I/O Locations, Configuring the Memory Interface Unit

For most designs, it is best to let FastChip make the first I/O assignment.  That way, FastChip optimizes the I/O assignment according to the CSL logic design.  However, not all designs have this luxury.  For example, the tutorial design example operates on one of the Triscend E5 development boards, which already have pre-defined pin assignments.

The output pads must be assigned to specific package pins on the E5 development board for the example design to correctly light up the LEDs.  The FastChip I/O Editor provides an intuitive, graphical interface to assign I/O pads to specific package pins.  Choose Constraints à I/O Editor from the FastChip menu.

FastChip displays the I/O Editor window.  All unassigned I/O pads are displayed in the “Available I/O Pads” area on the left.  The display on the right shows a graphical view of the selected package, with all pins numbered, labeled, and color-coded.  The legend in the lower left-hand shows the meaning of the color-coding.  Black pins are dedicated functions like JTAG, clocks, etc.  Ground connections are green; power connections are red.

Defining the Memory Interface Settings

The Triscend E5 CSoC has a Memory Interface Unit (MIU) that directly connects to most byte-wide static memories such a Flash, EPROM, or SRAM.  The static memory interface typically connects to an external Flash device containing the personality for the CSL programmable logic resources portion of the CSoC device and the compiled binary code for your design.

The MIU settings reserve the required pins in the I/O Editor.  If a MIU pin is not required for your application, the pin is released back to your design as a Programmable Input/Output (PIO) pin.  Invoke the MIU settings by clicking on the MIU button from the toolbar.

Define the static memory settings for this example application.  The E5 Evaluation Board has a 128Kx8 (1M-bit) Flash memory.  However, the evaluation board can be mounted on the development base board, which has a 512Kx8 Flash. Accordingly, select 512Kx8 from the dialog box.  This action reserves the required I/O pins in the I/O Editor.

Click OK when finished.

Assigning I/O Locations

Now that the MIU pins are reserved, start assigning the 7-segment LED driver outputs to the appropriate device pins.  To assign a pad to a package pin, first expand the Available I/O Pads tree and find the desired I/O.  Then, click and hold the left mouse button to drag the I/O pad.

 

While holding the left mouse button, drag the I/O pad to the desired pin location.

Once over the desired location, release the left mouse button to drop the pad.  Note that the assigned pin disappears from the Available I/O Pads tree.

There is another method to place PIO pins besides using drag-and-drop.  First, click the desired pin in the package window.  Then, select one of the assignable pads from the list.  Then click OK.

If you make an error, you can move the pad by dragging and dropping it onto another pin.   Likewise, you can drag an assigned pin back into the Available I/O Pads area.  Assign all pads to their respective package pins according to the following table.  This tutorial is primarily written for the Triscend E5 Evaluation Board.  However, the same design also functions on the XESS myCSoC board and the now-obsolete original E5 development board.

 

Module

Pad Name

E5 Evaluation Board

XESS myCSoC Board

Original E5 Development Board (obsolete)

D1

D1.SEGA

106

35

65

D1.SEGB

193

39

94

D1.SEGC

194

43

85

D1.SEGD

128

41

82

D1.SEGE

162

40

79

D1.SEGF

144

34

57

D1.SEGG

125

36

55

TOGGLER

TOGGLER.BEAT

135

44*

89

 

The decimal point segment on the XESS myCSoC board’s 7-segment display is not connected.  Use pin 44 to connect the TOGGLER.BEAT PIO pin.

Click OK after you finished assigning pads.  The I/O assignments are stored in a file called <project_name>.ioc, located in the project directory.  You may also edit the contents of this file using your favorite text editor.

STEP 8.  Bind the Project, Create Custom Hardware

In a process called Bind, FastChip compiles the design shown in the CSL window into to CSL logic within the CSoC device.  This process is analogous to the compile-link-load process when compiling a software program or the map-place-route process for creating a gate array or FPGA.

Bind is a computational-intensive process, much more so than a simple compiler for a processor.  Many complex computing algorithms optimize your design to fit it into the CSL logic.  The Bind process for this simple project may take five to ten minutes on computers that only meet the minimum system requirement. The status bar on the wait dialog box shows you how Bind is progressing.

The ultimate result from Bind is an initialization file called <project name>.csl.  This file is later combined with your software application image to download to the CSoC.

FastChip indicates the current Bind status for the project.  If Bind must be executed before completing the project, the Bind icon indicates, “Bind (not current)”.  If the Bind step has already been completed, the icon indicates just “Bind”.  To process the tutorial design, click the Bind icon.

Because Bind is compute-intensive, FastChip provides various Effort Levels allowing you to trade off compute runtime versus Bind quality of results.  The Maximum setting provides the best overall results but at significantly longer run times.  There is also a timing-driven mode where you can specify the timing requirements for your design.  Bind then attempts to compile the design and meet your requirements.  Again, this adds to the overall run time.

For this design, accept the default Bind effort level, Minimum, for minimum bind effort.

Then, click the Options tab.  Choose the Launch timing report option and the Remove gates … option.

As Bind progresses, you will see various messages in the output dialog box.

If you have not already licensed FastChip, you will see a message describing that you are currently running Bind in Evaluation mode.  The message also describes the limitation of the evaluation mode and how to obtain a FastChip license.  This tutorial design functions with either the full or evaluation modes.

Bind then performs a design-rule check (DRC) to find any potential problems.

Bind then performs automatic address allocation; similar to that when you generated the header file for your ‘C’ compiler.  This step finds all of the addressable items in your CSL designessentially anything using one of the CSoC’s address selectors.  Bind then assigns a physical address to every selector based on the design requirements such as address size and any relative address assignments specifying the address relationship between two or more selectors.

The mapping step decomposes your CSL logic design and then compacts the logic into the resources inside the CSL cells, the selectors, and the CSI bus resources.

The placement step determines the best location for each used CSL, selector, and bus resource out of the available resources on the selected target CSoC device.  This is analogous to the placement step of a printed circuit board place-and-route package.

The routing connections step decides how best to interconnect the CSL, selector, and bus resources given their current placement on the targeted CSoC device.

After completing the mapping, placement, and routing steps, FastChip performs a static timing analysis of all of the logic paths within the device.  These paths are described in detail when you generate a project report.

Bitstream generation creates the binary programming file for the compiled CSL design.  This file, called <project name>.csl, is used later to physically program the target CSoC device.

Finally, Bind reports that it successfully completed your design.

Click Close when finished.  The Bind result is saved in the <project_name>.csl file.  Because Launch timing report was check earlier, Bind launches your web browser to display the hyper-linked static timing report file.  For example, to see if the circuitry meets are the bus clock timing requirements, click Clock to Setup Delays.

The clock to setup delays are the time required for a signal to transfer from one register or flip-flop to another.  The delays paths are also listed by clock domain.  In this example, the worst-case clock to setup delay of 15.21 ns occurs when the RESULT register is read.  To see the details of which elements constitute the timing path, click the ‘X’ associated with the timing path, under the Details column.

The report shows the delay for each element in the path, and the sum for all the elements in the path.

Select File à Save Project to save the current state of the project. 

Note that the Bind button no longer indicates “(not current)”.  Also note that FastChip updates the resource estimates area with the exact resources as determined by Bind.  Before running Bind. FastChip quickly estimates CSL usage based on assumptions about the design.  After running Bind, FastChip knows exactly the CSL resources required.  If the values are different, it is usually only the number of CSL cells.

Before Bind …

 

After Bind …

 

View the Project Report

For more detailed information about your project, including register assignments, pin assignments, etc., select Generate Project Report from the Tools menu to display the project report dialog box.

Select Generate Project Report and click OK to create the project report.  You could also select “View Existing Report” to view a pre-created project report.

Click Close to invoke your default HTML browser to display the report file.

STEP 9.  Develop the Software Application

This design example uses Keil Software’s µVision2 C compiler for the 8051 microcontroller. This tutorial covers the features needed for this application.  Please refer to Keil’s documentation and tutorial for complete introduction of uVision2.

The C code is already written for you. If you copied the 3rdParty directory as requested earlier, the code is available in 3rdParty\Keil\main.c in your project directory.

The flow chart for the main program is shown below.

The code that implements this simple program is shown below.

 

// Include the header file automatically created by FastChip

#include "MyFirstE.h"

 

/************************************************************

* MAIN FUNCTION

************************************************************/

 

void main (void) {

 

   // Call the main initialization routine defined in the

   // included header file.

   MyFirstE5_INIT();

  

   while (1) {

 

     // Most embedded applications never stop executing.

     // Wait for Watchdog Timer interrupt to happen.

 

   }

}

 

The flow chart for the Watchdog Timer interrupt service routine (ISR) is show below.

The Watchdog interrupt service routine code appears below.

 

/***************************************************************

* Watchdog Interrupt Service Routine (ISR) *

* The interrupt vector for interrupt number 12 is at address 0x63

***************************************************************/

static void watchdogISR() interrupt 12 {

  

   // Increment the value in the RESULT register.  The Result register

   // connects to a 7-segment LED display.  Logic in the CSL matrix

   // converts the binary value in RESULT to the hexadecimal digit on

   // the LEDs.  

   RESULT = RESULT + 1;

 

   // Clear watchdog interrupt -- *** PROTECTED BY TIMED-ACCESS WINDOW ***

   TA = 0xAA;   // Open the timed-access window by writing 0xAA

   TA = 0x55;   //    followed by 0x55 to the TA register.

   // Timed-Access window now open for three instruction cycles.

   WDIF = 0;    // Clear the watchdog interrupt flag

   // Timed-Access window closed automatically.

 

   // Return from interrupt and continue to wait for next Watchdog

   // Timer interrupt.

}

 

The following section on using the Keil tools assumes that they are already properly installed on your computer.  Generally, it is best to install Keil before installing FastChip so that FastChip can configure various settings and copy over appropriate files.  The screen shots and behaviors shown are for Keil uVision 2.20a.

 

To compile the sample project, invoke the Keil µVision2 from the Start menu.

Select New Project… from the Project Menu.

Name the new project MyFirstE5.uv2. If you follow the directory structure as in the MyDesignE5 project, the Keil project should be saved inside the project directory under the 3rdParty\Keil directory.  Click Save.

Select Triscend à TE520 from the Select Device menu.

Right-click Source Group 1 in the File tab panel in the project window and select Add Files to Group ‘Source Group 1’.

Add main.c and MyFirstE.c to the project and click Close.  The files are displayed under Source Group 1 in the File tab panel in the project window.

Optionally, copy the Startup.a51 assembly routine from the C:\KeilC51\LIB\Triscend directory into your project directory.  This snippet of code is executed before branching to your C program.  This allows you to initialize memory locations as required by your application.  Otherwise, the Keil compiler uses the default Startup.a51 file.

STEP 10.   Compile and Link Your Software Application

A few uVision2 options must be configured before you can compile the application. Click Target and then right-click to reveal the menu.  Select Options for Target ‘Target 1’.

Most default selections in this dialog are acceptable.  You must make changes to the Output and Debug tab panels.

Output Tab

Click the Output tab.

Click the Settings button to configure the connection to the Triscend MultiJTAG Server (TMJS).  The default connection is shown below.

 

Click  to compile and link your project. You should see the following message in the message window at the bottom of the screen.

 

Built Target 'Target 1'

compiling main.c

compiling MyFirstE.c

assembline Startup.a51 …

linking

creating hex file from “MyFirstE5” …

"MyFirstE5" – 0 Error(s), 0 Warning(s)

STEP 11.   Invoke FastChip Device Link (FDL) Utility

In this section, the newly created design is converted into a configuration image to download and program the E5 CSoC device.

Preparing the E5 Target Board

Before attempting to download the design, be sure to properly prepare your E5 target board.  This example was written specifically for the Triscend E5 Evaluation Board.  However, the same design can also be used on the XESS myCSoC Board and the now-obsolete Triscend E5 Development Board.

Triscend E5 Evaluation Board/Development Platform

The example design operates using the E5 Evaluation Board stand-alone or when the evaluation board is mounted on the base board.  The setup procedure is identical in either case.

  1. Turn OFF power to the board.  If using the E5 Evaluation Board in stand-alone mode, the power switch is as shown in the diagram.  If the evaluation board is mounted on the base board, then the power switch is on the base board.
  2. Connect a printer cable between your computer’s parallel printer port and the parallel port on the evaluation board.

  1. Configure the option switch SW6 for downloading through the evaluation board’s parallel port.  Switch SW6.4 must be in the DOWN position and switch SW6.3 in the UP position.  Switches SW6.2 and SW6.1 do not matter.

  1. Ensure that jumper JP6 is installed.  The 7-segment LED will not light unless JP6 is installed.
  2. Re-apply power.

Continue with next step

XESS myCSoC Board

There are no special setup requirements for the myCSoC board.  Simply attach a 25-pin printer cable between your computer and the parallel port connector on the myCSoC board.  Plug in the AC adaptor to apply power.

 

The example design must be specifically modified to target the XESS myCSoC board.  The myCSoC board uses a different Triscend E5 than the Triscend E5 Evaluation Board and the 7-segment LED is connected to different pins.

 

Continue with next step

Original Triscend E5 Development Board

To download and debug the design on the original Triscend E5 Development Board, please follow these steps.

·         Turn off the power to the Development Board.

·         Connect the JTAG Download Cable to the parallel port on your PC. Connect the other end of the cable to the stake-pin header on the Development Board. Make sure that pin 1 on the cable is attached to pin 1 on the board. The socket on the board is not keyed. The red trace on the header should be along the top of the board. If the connector on the cable is narrower than the header on the board, leave the two pins closest to S1 unconnected.

·         Make sure that the power adapter is connected and plugged into the wall socket.

·         Switches SW1, SW4, and SW5, if assembled on your board, should all be set to "LOCAL". The switch arm for each switch should be toward the bottom edge of the board.

·         All the switched on DIP-switch package S2 should be switched toward "OPEN" (depressed toward the left edge of the board).

·         Reapply power to board.

Launch Triscend Multi-JTAG Server

Before launching FastChip, be sure to launch the Triscend MultiJTAG Server (TMJS).

TMJS allows you to download and debug an E5 design directly from your computer’s parallel port, or via another computer connected to your network.  Similarly, TMJS allows you to debug an E5 design via JTAG, even if the E5 device is part of a larger JTAG daisy-chain.

Once launched, TMJS stays persistent in memory until you power-down your computer or exit from the TMJS console window.

 

 

TRISCEND MULTIJTAG SERVER COMMANDS

help      : display Triscend MultiJTAG Server help.

exit/quit : disconnect target, terminate JTAG server & exit.

status    : show JTAG server connection status & settings.

connect   : launch JTAG server & connect to target.

terminate : disconnect target & terminate JTAG server.

clear     : clear target name & host port settings.

 

Launching JTAG server & connect to target 'TE5_Jtag_Wiggler' on port 5005

Server is running.

Opening TCP/IP channel to JTAG server on port 5005

TCP/IP channel is open.

 

 

Status  : Server is running.

Settings: TE5_Jtag_Wiggler, port 5005

 

tmjs<

Launch FastChip Device Link (FDL)

Use FastChip Device Link (FDL) to configure, program, and debug the CSoC.  With the MyFirstE5 project still opened, click the Device Link button to invoke the FastChip Device Link software.

FDL is designed to be a stand-alone program, separate from FastChip.  FDL can be installed as a stand-alone application on a computer in your development lab or on the manufacturing floor.

Once FDL loads, it displays a splash screen.

A welcome screen also appears describing the capabilities of FDL and how to execute FDL from a command line, minus the graphic interface.  If you wish, uncheck the Show this window … option box at the bottom of the dialog box to prevent this dialog from appearing the next time that you run FDL.  Click Close to continue.

The main FDL window should appear.  At this point, you may encounter an error dialog box indicating that FDL has No communication with the target.  You can continue to create a configuration file but you must correct the communication problem before you can download and debug your application.

If you wish to connect to the development board, double-check your board setup, make sure the TMJS is running, and click Retry.  Optionally, click OK to build a configuration file.  However, if FDL cannot communicate with the E5 target board, you will not be able to download or debug your application.

The most likely causes for the “No communication with target” message are …

When launched, the primary FDL window shows a list of observable items along the left edge of the screen and the currently monitored list along the right.

Step 12.  Create CSoC Configuration Image

Before actually downloading the design to the CSoC device, the Configuration step combines the CSL data created by Bind with software application image created by your 8051 compiler to create the final configuration file.  This is also the point where you specify where the configuration file will be stored and configure the clock source for the application.

To create a configuration file, click the Configuration icon from the FDL toolbar.

Set the configuration options as follows.

Target Memory Device:  Use the default setting CSoC Internal RAM to directly program the CSL, and place the application code into internal RAM.  Other options allow you to program an external Flash device over JTAG and to create a Hex for programming an external Flash or EPROM device using a dedicated device programmer.

CSI Bus Clock Source:  This tutorial is designed to operate on a variety of E5 development boards.  Consequently, use the Internal Ring Oscillator as the clock source as the ring oscillator is always available in an E5 application.

Enter the following file location to specify the output data file.

Triscend CSoC Configuration Image (.cfg):  FastChip combines the CSL configuration file and the processor code to create a final configuration image.  This file contains all the data necessary to configure the CSoC device on the development board.  By default, FDL saves the configuration image in the current project directory.  The configuration image can be saved as either a Triscend *.cfg file or as an Intel MCS-86 *.hex file, which is compatible with third-party device programmers for programming Flash and EPROM devices.

Enter the following file locations to specify the source data files of the design.

FastChip CSL Configuration File (.csl):  By default, this field points to the *.csl file created during the Bind process.  You can also select a specific *.csl file by clicking Browse.

Microprocessor Code (Intel Hex Format):  Click Browse and select the Hex file output from your 8051 compiler.

There is also an optional Security field where you can selectively disable JTAG access and the Memory Interface Unit (MIU) to prevent prying eyes from studying your application.  Select None to allow further debugging via JTAG.

After defining the configuration options, click Save and Download to save the configuration image and then automatically continue with the Download step.  Clicking “OK” saves the configuration image but does not download it.

FDL then combines the *.csl file created by Bind and the code image for the embedded 8051 processor created by your compiler.  The output is a configuration file, *.cfg.  The Configuration utility also creates a configuration report file, *.cfr that contains the register settings for the Memory Interface Unit (MIU) and clock configuration settings.

Click Close to continue with the Download step, described in the next section.  You must have a JTAG connection between the E5 development board and your computer before you can continue with this step.

STEP 13.  Download the CSoC Configuration Image

If you clicked “OK” when creating the Configuration image, click the Download icon to invoke the Download dialog box.  You must have a JTAG connection between the E5 development board and your computer before you can continue with this step.

Download allows you to download either a Triscend configuration file, *.cfg, or an Intel MCS-86 Hex file, *.hex.  During the Configuration step, we created a Triscend configuration file.  Use the default settings and click OK to start downloading to the CSoC on the development board.

When FastChip finishes downloading, you will see the 7-segment LED start counting up.  The display should update about twice per second.

The resulting dialog box shows the progress of downloading the design.  Click Close when downloading is finished.

STEP 14. In-System Debugging using the FastChip Device Link Utility

After you finish downloading the CSoC configuration data to the CSoC device, you should see the message “CSoC Running” in the status area in FastChip Device Link Utility. You can start performing in-system real time debugging using the FastChip Device Link Utility.

The E5 device—in conjunction with the FastChip Device Link utility and the JTAG connection—provides nearly unparalleled debugging capabilities.  Using the E5, you can debug your application …

The debugging capabilities of FDL supplement those of a good source-level debugger such as Keil dScope.  FDL is not intended to perform as a source-level debugger but provides capabilities not offered by a source-level debugger, such as the ability to monitor flip-flop and logic output values buried deep within the CSL logic.

Debug Tools

The FDL toolbar offers seven separate debugging functions.

The Breakpoint button allows you to set up the two hardware breakpoint units on the E5 CSoC.  Clicking this icon displays the breakpoint dialog box.

The Go button restarts program execution whenever the CPU is in reset, halted, or has reached a breakpoint.

The Stop CPU button halts the CPU execution when it is running.

The Reset button invokes a pull down menu offering the following options.

·         Reset the CPU only and halt it at the beginning of the application program

·         Reset the CPU only and start running the application program

·         Reset the entire CSoC device, and leave it halted.  If you downloaded to internal SRAM and select this option, you must download your design again.  If the configuration data was downloaded to external Flash, the CSoC device is staged to load itself from external Flash.

·         Reset the entire CSoC device and start the CSoC self-configuration process.  Again, if you downloaded the design to internal SRAM and select this option, you must download your design again.  If the configuration data was downloaded to external Flash, the CSoC device loads itself from external Flash and the CPU begins executing the application program.

The Single Step button executes the next assembly instruction pointed to by the current program counter, when the CPU is halted or at a breakpoint.  A single ‘C’-code statement may compile into multiple assembly instructions.  A source-level debugger, such as visionPROBE, allows you to single-step either assembly or ‘C’ instructions.

In addition to the buttons in the toolbar, there is also the Debug Watch window to display snapshot value of registers and nets within your FastChip project.

Observe and Control

Using FDL, you can monitor and control the E5 CSoC device from your computer via the JTAG connection.

Reads the value of the item selected in the watch window.

Reads the values of all items in the watch window.

Writes the value, if any is specified, to the selected item in the watch window.

Writes the values, if any are specified, for all items in the watch window.

Controls if and how often items in the watch window are automatically updated.  Useful for slowly changing values to monitor that the application is still operating.

While not intended as a real-time debugger for the 8051 microcontroller, FDL does provide some visibility into the 8051’s internal registers.   In the Debug Watch window, select the Type drop list under Observable Items and select CPU Registers.

Scroll down through the list of available registers to locate the program counter (PC) and select it.

To add the program counter, PC, into the list of watched items, click the plus-sign button while PC is highlighted.

The PC register appears in the watched items display along with three associated text boxes.  If the watched item appears on the CSI bus, the CSI Address is displayed.  The Observable Values text box displays the value read back from the PC register.  Use the Set to Value text box to modify the value of the associated item.  Not all items, such as network connections, can be modified.  Nets can only be monitored.

You are not limited to just monitoring CPU registers.  You can also watch any register that you added to the CSL matrix.  For example, the RESULT register was a new register created earlier in the tutorial.  FDL refers to these registers as Selector Registers because they use one of the CSoC’s Selector functions to decode the register’s address.

Again, in the Debug Watch window, click the Type list box under Observable Items. This time, however, choose Selector Registers.

Only one register appears in this list, RESULT.  Select the RESULT register and click on the green arrow, adding RESULT to the watched items display.

FDL now monitors the value stored in the RESULT register by reading RESULT at its assigned memory location.  However, there are times when you may not want to read the actual register.  For example, some peripherals have registers that are self-clearing when read.  Monitoring such registers may cause strange consequences during debug.

Another safe way to monitor the contents of a register is to monitor the nets connected to the flip-flops that form the register.  Monitor the output of the RESULT register by choosing Nets from the drop list.

Select the nets connected to the RESULT register, which is a bundle of nets called RESULT[3:0].  Again, click the green plus-sign to add these nets to the watched items display.

Every time you click the Read All button, the values in the Observable Values column are first read from the CSoC device via JTAG, uploaded to your computer, then displayed on your computer screen.  The RESULT command register display should match the number displayed on the LED on the board at the moment.

Click the Stop CPU button, and then click Read All to take a snapshot of the current device state.

To demonstrate how you can control logic buried deep inside the CSoC device over JTAG, double-click the entry from RESULT in the watch window.

Type the hexadecimal value “a” in the pop-up text box.

Then, click OK to download this value to the RESULT register.  You should see this new value reflected on the development board’s 7-segment LED display.

Now, add the Watchdog Timer values to the watch window.  The Watchdog Timer values appear under the “System Registers”.

Click Single Step a few times.  Observe the 7-segment LED display and PC register in the watch window.  In this case, you are single-stepping the 8051 microcontroller through a tight program loop.  The program is waiting in a while loop for the Watchdog Timer to expire so the program counter (PC) doesn’t appear to change.  However, notice that every click of Single Step increments the Watchdog Timer value.  Using this approach, it may take a few thousand mouse clicks to advance the program to the point where Watchdog Timer generates and interrupt and the 8051 increments the LED display.

A more productive approach is to set a breakpoint.

Setting Breakpoint

Next, setup a breakpoint to stop the CPU whenever the LED incremenys, using one of the CSoC’s built-in hardware breakpoints.  To do this, you need to know the address the RESULT register on the CSoC’s CSI bus.  The CSI Address for the RESULT register is displayed in the watch window.

FastChip allocated the RESULT register to address 0x0010_efff.  Now that you know RESULT’s assigned address, set up the hardware breakpoint.  Click on the Breakpoint button to display the breakpoint dialog box.  Check the Breakpoints Enabled option box.

Choose the Breakpoint 0 tab.  The RESULT register is read and written as a data access.  Select the Data Access option under Type.

In the Patterns panel, type “0x0010_efff” as the Address and “0xffff_ffff” as the Address Mask.  The underscore character (_) is just used as formatting and can be eliminated.  Setting the address mask to 0xffff_ffff indicates that we want to match all 32 CSI bus address lines.

For this step, ignore the data value on the bus by typing “0” for both Data and Data Mask.  Set  Access to Write.  This sets up breakpoint 0 to match a CSI write transaction to the RESULT register, regardless of the data value.  Click OK to define the breakpoint value.

Next, click the Go button a few times.  Note that the LED increments and stops.  Breakpoint 0 detects a write to the indicated address and halts the processor.  The status bar in the lower left-hand of the screen indicates “CSoC running.  CPU halted.”  Clicking the Go button restarts the processor and the status bar again indicates “CSoC running” until reaching the next breakpoint.

The two breakpoints units can be used independently or they can work together.  In the last example, Breakpoint 0 halted on any write transaction to the RESULT register.  This time, halt the processor only when there is a write access to the RESULT register and the data value is 0x5.

In the Breakpoint 0 tab, type “5” for the Data match value and “f” for the Data Mask value.

Now, click Go from the toolbar.  The LED should continue incrementing until it reaches “5”, then the system should halt.

Finally, click Breakpoint again to display the breakpoint dialog box.   Uncheck the Breakpoints Enabled box, and click OK.  Click Go to restart the processor, if it’s stopped.  Leave the FastChip Device Link Utility running.

Observing Memory

To view a range of memory locations, click the Memory View button.

Then, select the desired Address Space.  In this example, view the 8051’s 256-byte DATA/SFR space, which starts at address 0.  It may appear that the data is duplicated multiple times because FastChip reads a minimum of 1K bytes.  The 256-byte region appears four times.

Click Refresh to update the memory values and Close to dismiss the window.

STEP 15.   In-System Debugging using the Keil Debugger

FastChip Device Link Utility also enables you to perform software debugging using Keil’s dScope symbolic debugger.  All typical software debugging features, such as single step, set breakpoints, watch variables, display stack and display memory can be performed in-circuit on the development board, without the overhead of purchasing an expensive emulator.

In the uVision2 source code display window, scroll down in the code window and double-click the instruction RESULT = RESULT + 1;.

A breakpoint is inserted before the source line, indicated by the red rectangle icon.  Since a breakpoint is associated with a specific line number, the breakpoint stays in effect even if the code is changed and recompiled.

While your development board is running, click  to start a debug session.

Now, if you click , the code runs until it hits your breakpoint and stops.

Click Window --> Tile Horizontally to display the code and the disassembly window.

The source code window is exactly the same window as the one you used in the editor. The only change is that code lines that actually generated executable code are identified through a solid gray block in the left-hand margin. The yellow arrow shows the program counter when code execution is halted.

The other window is a disassembly window. By default, it is set up to show source code and the assembly code generated by compiler and linker. If you single step while this window is active, you will single step one assembly instruction at a time. If you single step in the source code window, the debugger will step one C code line at a time.

Click  to activate the Watch window. Click the Watch#1 tab, click the highlighted field and press function key F2.

 

Type RESULT and press <Enter>.

Continue to run by pressing the run button repeatedly. Note that RESULT increments by one every time you stop at the breakpoint. The RESULT value displayed on the screen matches the value on the 7-segment LED.

You have now completed Part 1 of this tutorial. The next part of this tutorial will introduce you to the FastChip command line interface.

PART II  Design with FastChip Command-Line Interface

All functions in the FastChip's Graphical User Interface (GUI) are also available through the FastChip command line interface.  All FastChip commands are accessible through csoc.exe found in the <FastChip Installation Directory>\fastchip\bin directory.  Most of the Triscend supported third-party design tools also include command-line or batch-file interfaces.

Graphical and command line FastChip interfaces are useful for different kinds of design activities.  The graphical interface is useful for tasks performed rarely, such as entering a design, instantiating and parameterizing a soft module library, connecting modules, etc.  The command interface, by contrast, is useful for RTL design flow, and automating repetitive tasks.

The power of the command line is truly unleashed when multiple commands are chained together in a script file.  With scripts—such as DOS batch script, shell script, perl script or makefile—repetitive tasks become manageable, if not automatic.

A script can generate headers, compile C code, and link the microprocessor code.  A script can also run logic synthesis tools on an RTL design, import the result into FastChip, bind, export and verify the resulting design against a simulation test bench.  Likewise, a script combine the microprocessor code with the CSL configuration file and download the result to the CSoC under test.  Finally, a script can perform in-circuit debugging of hardware and software design as part of a regression suite to ensure that an application still functions correctly after a design iteration.

Unlike other scripting solutions, make files provide the capability to specify dependency between different files.  It is very convenient to rerun only the changed portion of a design once the dependency is setup correctly.

Triscend FastChip ships with a number of demonstration projects with makefiles included.  Makefiles are commonly used during software development, particularly by command-line tool users.  However, there are many similar but not mutually compatible makefile tools available.  Triscend chooses GNU make as the reference standard for the project makefiles.

GNU make is part of the popular GNU free software available on many operating system platforms, including many variants of UNIX and Microsoft Windows.  The GNU tools are available from GNU's web site at http://www.gnu.org.  The Cygwin tools are ports of the popular GNU development tools and utilities for Windows 95, 98, 2000 and NT (http://sources.redhat.com/cygwin).

Only a very small subset of the cygwin tools is needed in order to use the bundled makefiles.  For users’ convenience, only the selected subset is offered in the directory ThirdParty\Redhat\cygwin\bin.  We recommend users to copy the entire \cygwin directory and its \bin sub-directory to C:\ on the hard disk.  Also, add "C:\cygwin\bin" to your Windows PATH environment variable.

To comply with the GPL license, Triscend re-distributes the unmodified binary and source files on the FastChip CD-ROM under the Thirdparty\Redhat\cygwin_install directory.  The complete Cygwin package can be installed by running "setup.exe" directly from that directory on the CD-ROM.  If "cygwin\bin" has been installed previously, there is no need to run "setup.exe" again.

Windows PCs running the McAfee anti-virus software may generate warning or error messages on some of the .tar.gz files when the cygwin_install directory is copied from the CD-ROM to a hard disk. Apparently, the anti-virus software is cautious about a non-Windows-native compression format it doesn't quite understand. Turn off checking on compressed files to proceed with copying if desired.

The third portion of the tutorial assumes that the user is a fairly advanced PC user who is comfortable with using the MS-DOS command shell and DOS batch files. In this exercise, you will add some functionality to the source code and change the design. You will use the command line interface to compile, link, bind and download the code into the E520.

DOS Environment Variable

To use the FastChip command line, the FastChip \bin directory must be in your executable search path.  FastChip installation software automatically sets this environment variable for you.  You can double check this variable by typing

set path

in a DOS command window, and make sure the FastChip bin directory is in the printed text.  You can also type:

csoc

to see if the csoc general help message is displayed.  If the search path is not setup properly, you can set it yourself by typing the following.  This assumes that FastChip was installed in the default location under C:\Triscend.

set PATH=C:\Triscend\FastChip\bin;%PATH%

In addition to running FastChip from the command line, Keil’s uVision2 can also be run from the command line.  However, the following environment variables must be setup first.  This assumes that Keil was installed in the default location, C:\Keil.

set PATH=C:\Keil\c51\bin;%PATH%

SET C51INC=C:\Keil\C51\INC;C:\Triscend\FastChip\INCLUDE

SET C51LIB= C:\Keil\C51\LIB

Creating a DOS Batch File for the MyFirstE5 Project

Use your favorite editor to create a batch file called BUILDALL.BAT inside your MyFirstE5 project directory, and include the following line.

csoc generate MyFirstE5.fcp –dir 3rdParty\Keil

 The generate command generates the MyFirstE5 project header and source files in the 3rdParty\Keil directory.  This command is useful when you change the dedicated resource parameterization and want to propagate the changes to the microprocessor code.  Once the new project header and source files are generated, run the Keil compiler, linker and hex file generator to create an Intel Hex image for downloading to the Triscend CSoC device.  The following commands do exactly these steps.

cd 3rdParty\Keil

c51 main.c DEBUG OBJECTEXTEND

c51 MyFirstE5.c DEBUG OBJECTEXTEND

a51 Startup.a51

bl51 main.obj, MyFirstE.obj, Startup.obj to MyFirstE5.abs

oh51 MyFirstE5.abs HEXFILE(MyFirstE5.hex) cd ..\..

In case the Heartbeat module is changed, re-import the EDIF file into the FastChip project.  The following FastChip import command performs this step.

csoc import MyFirstE5.fcp -reimport heartbeat

After re-importing the Heartbeat module, Bind the FastChip project again.

csoc bind MyFirstE5.fcp

The microprocessor code image and the CSL configuration data produced by the bind command is combined with CSoC boot code and stored as the CSoC configuration image file.

csoc config -code 3rdParty\Keil\MyFirstE5.hex -csl MyFirstE5.csl -mem NONE -clk ring -dev E520 -out DIRECT.hex

Use the FastChip download command to program the CSoC configuration image file onto the E5 target board.  The Triscend Multi-JTAG Server (TMJS) must be running from a separate command window or DOS box in order to make the connection.

csoc download DIRECT.hex -dev E520 -mem NONE –pgm

Furthermore, you can issue various test commands to the target hardware using the csoc debug command.  The following command issues various debugging commands over the JTAG connection with the E5 CSoC device.  The sample file, shown below, resets and halts the 8051 microcontroller, reads the RESULT register, and then verifies various write operations to the RESULT register.  Finally, the 8051 is reset and restarted.  Obviously, this is merely a simple example of the potential capabilities.

csoc debug -dev E520 -xref MyFirstE5.xref -options MyDebugCommands.cmd

MyDebugCommands.cmd File

resetcpu

readmem RESULT

writemem RESULT=0xa

verifymem RESULT=0xa

writemem RESULT=0x5

verifymem RESULT=0x5

resetcpu

go

Modifying the MyFirstE5 Project

Assume there is a design requirement change. Now, instead of incrementing the LED display by 1 every second, you want to increment it by 3.  This is a one-line code change in the main.c source file.

Using your favorite editor, change the line in main.c from:

RESULT = RESULT + 1;

to

RESULT = RESULT + 3;

After making the code change, save the main.c file.

Running BUILDALL.BAT

From the DOS command window where you already setup the environment variables, first change directory into the MyFirstE5 project directory, where you have created the DOS batch file BUILDALL.BAT.  Then type:

BUILDALL.BAT

You will see in the DOS windows messages about different commands being executed, and the output results from each program.  By the end of the batch file, you will see your demo board start counting up in increments of three, instead of one.

Running the command lines via a batch file works fine. However, this is far more primitive and less efficient than the results obtained with a well configured make file. In our case, generate, compile, link and bind are always performed no matter what changes have been done.

You can improve the flow by breaking the batch file into multiple batch files, and call them individually when the need arises.  For example, in the MyDesignE5 sample design directory, you can find the following pre-build batch files.

BUILDALL.BAT File

echo off

echo ***********************************

echo *** MAKEFILE for MyDesignE5

echo ***********************************

echo .

echo TMJS must be running so that the design can communicate

echo with the Triscend E5 target board.

echo Run TMJS by typing "tmjs -a e5" in another command window.

echo .

pause

echo .

cd c:\Triscend\Projects\MyFirstE5

echo .

echo Generate header file ...

csoc generate MyFirstE5.fcp -dir 3rdParty\Keil

echo .

echo Compile application program ...

cd 3rdParty\Keil

c51 main.c DEBUG OBJECTEXTEND

c51 MyFirstE.c DEBUG OBJECTEXTEND

a51 Startup.a51

bl51 main.obj, MyFirstE.obj, Startup.obj to MyFirstE5.abs

oh51 MyFirstE5.abs HEXFILE(MyFirstE5.hex)

cd ..\..

echo .

echo Update Heartbeat imported module to latest revision ...

csoc import MyFirstE5.fcp -reimport heartbeat

echo .

echo Bind design to update CSoC hardware ...

csoc bind MyFirstE5.fcp

echo .

echo Create configuration image ...

csoc config -code 3rdParty\Keil\MyFirstE5.hex -csl MyFirstE5.csl -mem NONE -clk ring -dev E520 -out DIRECT.hex

echo .

echo Download configuration image ...

csoc download DIRECT.hex -dev E520 -mem NONE -pgm

echo .

echo .

echo DESIGN SHOULD NOW BE RUNNING!!!

echo .

echo Launching CSOC DEBUG to perform basic hardware tests ...

echo  - Read commands from MyDebugCOmmands.cmd

echo  - Reset CPU and halt the target

echo  - Read current value of RESULT register

echo  - Write RESULT register with 0xa

echo  - Verify RESULT contains 0xa

echo  - Write RESULT register with 0x5

echo  - Verify RESULT contains 0x5

echo  - Reset CPU again

echo  - Run program

csoc debug -dev E520 -xref MyFirstE5.xref -options MyDebugCommands.cmd

 

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