Steven K. Knapp
Steve's broad, multidisciplinary experience produced results across a range of technologies and businesses. The following links provide a sample.
User Guides
Lattice Semiconductor iCEman40-HX8K Evaluation Kit User Guide
Lattice Semiconductor iCEblink40-HX1K Evaluation Kit User Guide
Lattice Semiconductor iCEblink40-LP1K Evaluation Kit User Guide
SiliconBlue iCEman65P Evaluation Kit User Guide
SiliconBlue iCEman65L Evaluation Kit User Guide
Xilinx® Spartan®-3AN In-System Flash User Guide
Xilinx Spartan-3 Generation Configuration User Guide
Xilinx Spartan-3 Generation FPGA User Guide
Xilinx Spartan-3A Starter Kit Board User Guide
Xilinx Spartan-3E Starter Kit Board User Guide
Xilinx Spartan-3 Starter Kit Board User Guide
Xilinx PicoBlaze™ 8-bit Embedded Microcontroller User Guide
Xilinx LogiCore™ PCI Master and Slave Interface User's Guide
Silistix®: CHAIN™ Network Performance Closure and Verification User Guide
Silistix: CHAIN Network Adapter User Guide for ARM® AMBA® APB, AHB, AXI bus interfaces and the Open Core Protocol (OCP) bus interface
Silistix: Describing a System Using Connection Specification Language (CSL™)
Silistix: Building and Analyzing On-Chip Networks using CHAIN®architect
Triscend: Triscend E5 Hardware Development Platform User Manual
Data Sheets
Steve created the following data sheets including most of the technical illustrations
SiliconBlue iCE65L Ultra-Low Power Programmable Logic Family
SiliconBlue iCE65P Ultra-Low Power Programmable Logic Family
SiliconBlue iCE65L04 iCE DiCE Data Sheet
SiliconBlue iCE65L08 iCE DiCE Data Sheet
Xilinx Spartan-3AN FPGA Family Data Sheet
Xilinx Spartan-3A FPGA Family Data Sheet
Xilinx Spartan-3E FPGA Family Data Sheet
Xilinx Spartan-3 FPGA Family Data Sheet
Triscend™ A7S Configurable System-on-Chip Platform (ARM7TDMI)
Triscend E5 Configurable System-on-Chip Platform (8051/8052)
Books
Development/Evaluation Boards
Steve specified and, in many cases, either managed development of or documented the following development or evaluation boards.
Application Notes
Lattice Semiconductor TN1253: Using Differential I/O (LVDS, Sub-LVDS) in iCE40
SiliconBlue AN014: iCE65 mobileFPGA as an LVDS, FPD-Link Display Driver
SiliconBlue AN016: Dual-Row QFN Package Assembly and PCB Layout Guidelines
SiliconBlue AN012: iCE65 FPGA Low Power Design Guidelines
SiliconBlue AN010: iC65 Printed Circuit Board (PCB) Layout Guidelines
SiliconBlue AN008: Using Differential I/O (LVDS, SubLVDS, LVPEC) in iCE65 mobileFPGAs (all except layout requirements section)
Differential I/O Spreadsheet
Xilinx XAPP477: Embedded Processing and Control Solutions for Spartan-3 FPGAs
Xilinx XAPP462: Using Digital Clock Managers (DCMs) in Spartan-3 FPGAs
Xilinx XAPP463: Using Block RAM in Spartan-3 Generation FPGAs
Triscend AN02: Impementing Secure Remote Updates using Triscend E5 Configurable System-on-Chip Devices
AN02 code source files (ZIP)
Triscend AN07: Using Keil Development Tools with Triscend FastChip and the E5 CSoC Family
Xilinx XAPP065: XC4000 Series Edge-Triggered and Dual-Port RAM Capability
Xilinx: Fully Compliant PCI Interface in an XC3164A-2 FPGA
Xilinx: A Plug and Play Interface Using Xilinx FPGAs
The next three application notes first appeared as chapters in The Programmable Gate Array Design Handbook, Xilinx, First Edition, 1986.
Xilinx: Counter Examples
Xilinx: Ins and Outs of Logic Cell Array I/O Blocks
Xilinx: A Seven-Segment Display Driver
The following application note also appeared in the Intel Memory Design Handbook, 1986.
Intel AP-187: MEGABITS TO MEGABYTES: Bubble Memory System Design and Board Layout
White Papers
Altera: Architecture Matters: Choosing the Right SoC FPGA for Your Application (2013)
Altera: Real-Time Challenges and Opportunities in SoCs (2013)
Opal Kelly: Semiconductor Evaluation Leveraging
COTS FPGAs and Connectors (2012)
Altera: SoC FPGA ARM Cortex-A9 MPCore Processor Advance Information Brief (2011)
Altera: SoC FPGA Dedicated Peripherals Advance Information Brief (2011)
Xilinx XC5200 vs. Altera FLEX 8000A FPGAs (1996)
XC4000-Series FPGAs: The Best Choice for Delivering Logic Cores (1996)
Conference Papers
FPGA Summit 2008:
Session organizer for Tutorial 2A: Getting Your FPGA Application Up and Running, author and speaker for "Test Tools and Equipment" portion.
DesignCon 2000:
A Configurable System-on-Chip Device Facilitates Customization and Reuse
Presentation Slides
Custom Integrated Cicuits Conference (CICC 2000):
Field Configurable System-on-Chip Device Architecture
Presentation Slides
Embedded Systems Conference (ESC 1999):
Rapidly Developing Embedded Systems Using Configurable Processors
Presentation Slides
Embedded Systems Conference (ESC 1998):
Configurable Embedded Systems: Using Programmable Logic to Compress Embedded System Design Cycles
Presentation Slides
Design SuperCon 1997:
Designing a PCI Target/Initiator in FPGAs
Silicon Valley PC Conference:
Using LogiCore Modules for PCI Card Design
Asian EE PLD Conference:
Using Programmable Logic to Accelerate DSP Functions
Programmable Logic Breakthrough 1995:
Hot Applications: PCI, Plug and Play, PCMCIA
Wescon 1991:
Module Generators for Xilinx Field Programmable Gate Arrays
Wescon 1988, Electro 1988:
Optimizing Programmable Gate Array Designs
Patents
Steve has 14 patents issued to date, with other filings in progress at the U.S. Patent and Trademark Office.
- US Patent #5422833: Method and System for Propagating Data Type for Circuit Design from a High Level Block Diagram
- US Patent #5499192: Method for Generating Logic Modules from a High Level Block Diagram
- US Patent #5553001: Method for Optimizing Resource Allocation Starting from a High Level
- US Patent #5574655: Method of Allocating Logic Using General Function Components
- US Patent #5617573: State Splitting for Level Reduction
- US Patent #5737234: Method of Optimizing Resource Allocation Starting from a High Level Block Diagram
- US Patent #6691266: Bus Mastering Debugging System for Integrated Circuits
- US Patent #7243227: Method and Apparatus to Copy Protect Software Programs
- US Patent #7281082: Flexible Scheme for Configuring Programmable Semiconductor Devices Using or Loading Programs from SPI-based Serial Flash Memories that Support Multiple SPI Flash Vendors and Device Families
- US Patent #7358762: Parallel Interface for Configuring Programmable Devices
- US Patent #7454556: Method to Program non-JTAG Attached Devices or Memories Using a PLD and Its Associated JTAG Interface
- US Patent #7535249: Authentication for information provided to an integrated circuit
- US Patent #7768293: Authentication for information provided to an integrated circuit
- US Patent #7987358: Methods of authenticating a user design in a programmable integrated circuit
Web-Based Projects
EasyReadTools.com Web Site (2012)
Managed logo creation, developed site look and feel, and wrote portions of the content.
Triscend Configurable System-on-Chip Learning Center (1998)
Although embarrassingly simple by today's standard, this project was one of the early attempts at web-based customer training.
Triscend SupportCenter (1999-2002)
Originally, these answer records were part of a larger KnowledgeBase.net customer self-support website. This website helped customers using Triscend E5 or A7 silicon devices and the Triscend FastChip development system.
Articles about Triscend SupportCenter:
Nikkei Internet Technology (December 2000) [Japanese]
Customer Support Management (July/Aug. 2000): Mind Your Own Business
Tutorials
Building a Working Design Example Using the Triscend A7 Evaluation Board
Triscend FastChip 2.3.0 Tutorial for the E5 CSoC Device
Electronic Design and Intellectual Property (IP) Core Development
Multifunction Embedded DSP Block for iCE40 ultra-low-power FPGAs (SB_MAC16). Architected and specified a compact design supporting 350 MHz+ performance while fitting within the existing contraints of the iCE65/iCE40 block and interconnect structure. Supports 16x16 or 2x8x8 mutliplies, 32- or 2x16-bit add/subtract/accumulate, 32- or 2x16-bit variable-modulo, preloadable up/down binary counters, comparators, multiplexers, etc. Now in full production as part of the Lattice Semiconductor iCE40 Ultra low-power FPGA product family.

Cascadable Embedded Block RAM Columns. Architected and specified a cascadable interconnect structure to create selectable memory arrays based on a segmented column of 256x16 embedded RAM blocks. Reduces interrconnect congestion and improves system performance. Now in full production as part of the SiliconBlue/Lattice Semiconductor iCE40 product families.
FPD-Link Display Interface for iCE40 and iCE65 FPGAs. Developed high-speed 7-to-1 serializers using FPGA logic in iCE40 and iCE65 FPGAs. Careful layout and deep architectural knowlege was required for maximum performance. Created an 6:6:6 and 8:8:8 FPD-link flat-panel interface in Verilog. Created a graphics timing generator to drive various displays. Eventually, drove an 18-bit-per-color (6:6:8) 1,366x768 flat-panel display using existing 5Mpixel camera IP to create a live-action demonstration on the SiliconBlue iCE40HX and Lattice Semicondutor iCEman40HX engineering boards.

FPGA-based GSM A-bis Cell-Phone Traffic Optimizer. With Engage Communication, developed low-level architecture to compress and process up to 512 simultaneous EFR and ER full-rate GSM conversions (TRAU slots) using a single Spartan-3A FPGA. The design heavily utilizes time-division-multiplexing (TDM) techniques to reduce FPGA resources. The context for each of the 512 channels is stored within the FPGA's block RAM. The design and testbenches were created in Verilog and additonal hardware testing performed using a GSM traffic emulator and recorded call traffic.

Capacitive Touch Buttons and Virtual Hardware for Low-Cost Evaluation Board. To reduce cost on a low-cost "bare-bones" FPGA development board, toggle and pushbutton switches were eliminated and replaced with capacitive touch buttons controlled by FPGA hardware.

Each of the capacitive touch buttons has an associated resistor plus the capacitor created by the touch button pad itself. Touching a button increases the total capacitance of the button and lenghtens its associated RC delay. The FPGA circuit measures and discriminates between a touched and untouched button.

Similarly, other board I/O functions are replaced--including buttons, switches, LEDs, and values--by a computer connected to the board's USB programming, power, and debugging connector. A logic function built in the FPGA and software running on the PC translates the virtual I/O values into real values on the FPGA board. The design is described in more detail, including the associated Verilog code, here.

Technical Training
Data I/O Azido (2011)
FPGAs: More than you really wanted to know
("Desktop publishing" ... but for logic) (2011)
A Quick Tour of Data I/O Azido (2011)
A Drive Through Data I/O Azido (2011)
An Introduction to the Scratch Programming Language for Education (2011)
SiliconBlue: iCE65 FPGA Architecture (2008)
SiliconBlue: iCEman65 Board (2008)
SiliconBlue: Introduction to VHDL/Verilog (2008)
Introduction to the Xilinx Spartan-3E Starter Kit (2006)
Spartan-3E FPGAs for Lowest Total Cost: Configuration Options (2005)
Secrets of the DCM: Part I (2004)
Secrets of the DCM: Part II (2004)
Triscend A7 Configurable System-on-Chip Hardware Overview
Triscend FastChip 2.1.2 and A7 Configuration System-on-Chip FAE Training
Triscend E5 Configurable System Interconnect (CSI) Bus
Triscend E5 Configurable System-on-Chip
Articles (by Steven K. Knapp)
XCell Journal (2nd Quarter, 2005):
Implementing New Configuration Options for the Spartan-3E Family
Personal Engineering (Dec. 1998):
FPGAs furnish fast, furious FIR filters
Personal Engineering (Oct. 1998):
Parallel processing in FPGAs rivals DSP speed
Personal Engineering (July 1998):
Constant-coefficient multipliers save FPGA space, time
Personal Engineering (May 1998):
FPGA lookup tables build flexible pattern matchers
Personal Engineering (Mar. 1998):
Programmable logic overcomes processor bottlenecks
Personal Engineering (Jan. 1998):
In HDLs, what you see isn't always what you get
Personal Engineering (Nov. 1997):
KISS those asynchronous-logic problems good-bye
Personal Engineering (Sept. 1997):
Support options for programmable logic don’t differ much from board design
Personal Engineering (July 1997):
Understanding programmable logic means digesting its alphabet soup
Electronic Products & Technology (ep&t) (Sept. 1996):
FPGAs Tackle Multimedia, Communications DSP Jobs
Elektronik Informationen (November 7, 1991):
Onchip RAM erhöht die Logikkomplexität in FPGA
Electronic Design (Sept. 1990):
Accelerate FPGA Macros with One-Hot Approach
Electronic Engineering Times (EE Times) (May 1987):
The Acid Test
Electronic Design (Aug. 1985):
Once a difficult task, bubble memory design is now a question of layout
Solutions (Sept./Oct. 1985):
Megabits to Megabytes: Bubble Memory System Design and Board Layout
Articles (about Steven K. Knapp)
Customer Support Management (July/Aug. 2000): Mind Your Own Business
The article describes the Triscend SupportCenter web-based technical support system designed and created by Steve Knapp in association with SafeHarbor Technology and KnowledgeBase.net.
Software Manuals and Guides
SiliconBlue: Adept Programming Software and ICEUTIL.EXE Installation Guide
Triscend: Using the Triscend LiteLoader Software
Xilinx: X-BLOX Reference/User Guide
Although Steve did not format or compile the material for this manual, he provided major portions of the material. He was the overall architect and manager for the X-BLOX project.
Keywords:
FPGA, field programmable gate array, programmable logic, CPLD, EPLD, configurable, system-on-chip, SoC, CSoC, embedded, processor, microcontroller, 8051, 8052, 8031, 8032, E5, ARM7, ARM9, ARM7TDMI, FastChip, XACT, ISE, Spartan-3, Spartan-3E, Spartan-3A, Spartan-3AN, iCE65, starter kit, tutorial, bubble memory, Xilinx, Triscend, SiliconBlue, Intel, Silistix, Engage Communications, Element CXI, Azido, Data I/O, SiliconBlue, Lattice Semiconductor, Lattice, X-BLOX, block RAM, BRAM, DCM, DLL, boards, evaluation kit, patent, X-BLOX, logic synthesis, Flash, SPI, security, configuration, PCI, LogiCore, Plug-n-Play, SupportCenter, IP, intellectual property, SoC FPGA, Zynq
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